In a semiconductor field, a three dimensional structure technology is becoming a focus in order to fabricate a highly integrated chip. For instance, a memory chip with a multi-layer stack structure is an important technical trend in high density storage. For a fabrication of a device with the multi-layer stack structure, according to one method, firstly a semiconductor structure with a plurality of insulation dielectric layers and a plurality of single crystal semiconductor layers alternately stacked is formed, and then a device is formed on the single crystal semiconductor layer.
However, the fabrication the semiconductor structure with a plurality of insulation dielectric layers and a plurality of single crystal semiconductor layers alternately stacked has not been well developed yet for decades. A main reason is that a common single crystal semiconductor material is difficult to lattice match with a conventional insulation dielectric material. A common method for forming a single crystal semiconductor film is an epitaxial growth. For the epitaxial growth of a high quality single crystal semiconductor film on the insulation dielectric, the insulation dielectric material may be required to not only have a single crystal structure, but also well lattice match with the single crystal semiconductor film. Taking a commonly used single crystal silicon as an example, most known insulation dielectric materials have an amorphous structure or lattice constant differences between these currently known insulation dielectric materials and silicon are large. For instance, although conventional insulation dielectric materials (such as SiO2, Si3N4, HfO2, ZrO2 or Al2O3) may form single crystals, the lattice constant differences between them and the single crystal silicon are large. Many defects will be produced in the single crystal silicon film which is epitaxially grown on these single crystal dielectric layers, or even it is difficult to epitaxially grow the single crystal silicon film, thus resulting in a defective device formed on the single crystal silicon film.
In addition, with an increase of an integration density of semiconductor devices, heat dissipation will become a critical problem. Particularly, for a three dimensional logic device, a heat conductivity of an isolation dielectric filled between devices is required to be the larger the better so as to improve a performance of the logic device. However, the heat conductivity of a conventional insulation dielectric (such as SiO2 or SiOxNy) is too poor to satisfy a heat dissipation requirement of a high density integrated semiconductor logic chip.